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제목 [IT기술세미나 수업]Advanced Semiconductor Technology: From “Small Change” to “Deep Change”- 신창환 서울시립대 교수
작성자 수업담당 작성일 2017-09-26

[IT기술세미나 수업]Advanced Semiconductor Technology: From “Small Change” to “Deep Change”
- 신창환 서울시립대 교수


9월 26() IT기술세미나 수업은 아래와 같이 진행됩니다.


(IT기술세미나 수업은 전공분야의 내용을 영어로 하는 수업이며, 대학원 수업이지만 수강생 여부와 상관없이 학부생도 참여가능하오니 관심있는 모든 학생들이 참여해 주시기 바랍니다.)


- 세미나 연 사 : 신창환 서울시립대 교수


※ Biography


[Education]

2000 ~ 2006 EE, Korea University (B.S.)

2006 ~ 2011 EECS, University of California Berkeley (Ph.D.) (Advisor: Tsu-Jae King Liu)


[Experience]

2017 ~ now Director (Audit Committee), SK hynix

2016 ~ now Associate Professor, ECE, University of Seoul

2012 ~ 2016 Assistance Professor, ECE, University of Seoul

2011 ~ 2012 Xilinx Inc. (San Jose, CA, USA)

2010 ~ 2010 IBM Corp. (East Fishkill, NY, USA)


- 세미나 일 시 : 2017. 9. 26()

- 세미나 시 간 : 오후 5~ 550분까지

- 세미나 장 소 : 1공학관 23219

- 세미나 내 용 : Advanced Semiconductor Technology: From “Small Change” to “Deep Change”



Advanced Semiconductor Technology: From “Small Change” to “Deep Change”


Changhwan Shin, Ph.D.


Associate Professor, Department of Electrical and Computer Engineering, University of Seoul, Seoul, Korea

Director, SK hynix, Icheon, Korea


Silicon-based semiconductor technology has significantly changed the way we live. Since hand-held mobile electronic devices including smart phone are developed, human life has become more convenient and connected to everything, so that the era of “hyper-connected society” has been opened. The fundamental infrastructure of the society should be built on the semiconductor technology, especially complementary metal oxide semiconductor (CMOS) technology. As CMOS device is being scaled down over the past a few decades, the state-of-the-art CMOS technology platform has been touched down to ~ 10 nm technology node with commensurate performance improvement. Notwithstanding many technical solutions such as stress engineering, high-k/metal-gate, and three-dimensional device structure (e.g., Fin-shaped Field Effect Transistor, or FinFET) for aggressively scaled technology nodes, semiconductor industry is currently faced with a major technical problem as below:


(1) Incommensurate scaling of power supply voltage (VDD) for every CMOS generation, because of the fundamental limit called “Boltzmann Tranny” (i.e., subthreshold slope > 60 mV/decade at 300 K, resulting in soared-up power density in IC). In order to overcome the physical limit in CMOS devices, negative capacitance field effect transistor (NCFET) with ferroelectric material has been proposed and considered as one of the alternatives. In this IT seminar, the super steep switching device technology using the negative capacitance is to be introduced with the silicon data of negative capacitance MOSFET.


(2) Process-induced random variation: the process-induced random variation in threshold voltage (VT) provoked the nonnegligible VT mismatch in the bit cell of the static random access memory (SRAM) because the bit cell employed state-of-the-art transistors (i.e., the smallest transistors in physical size). The line-edge roughness (LER)-/random dopant fluctuation (RDF)-/workfunction variation (WFV)-induced VT mismatch in SRAM cells obscured the scaling of the operating voltage, resulting in increased power density in the SRAM. Hence, a variation-immune device design to minimize the process-induced VT variation as well as to improve the gate-to-channel control for reducing the short channel effects (SCEs) becomes important, whereupon some alternative designs of thin-body device structure are considered (e.g.,fully depleted silicon-on-insulator (FD-SOI) MOSFET, FinFET, and Tri-gate MOSFET). However, these advanced device structures impose certain additional expenses to use the silicon-on-insulator (SOI) substrate and have relatively complicated fabrication processes as compared to the conventional planar bulk MOSFETs. To address the aforementioned issues, a quasi-planar trigate (QPT) bulk CMOS transistor was designed to alleviate the process-induced random variation with reasonable cost and simple fabrication steps.


In this talk, a few previous studies on how “Small Change“ in device technology would lead “Deep Change“ in semiconductor technology are to be discussed in detail.